메뉴 건너뛰기




Volumn , Issue , 1999, Pages 51-56

Application of supply current testing to analogue circuits, towards a structural analogue test methodology ?!

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUITS; COST EFFECTIVENESS; COST REDUCTION; DIGITAL SUBSCRIBER LINES; MODEMS; TELEPHONE LINES; TIMING CIRCUITS;

EID: 0142257981     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ETW.1999.804221     Document Type: Conference Paper
Times cited : (6)

References (11)
  • 1
    • 85040072375 scopus 로고    scopus 로고
    • Towards an effective IDDO test vector selection and application methodology
    • October 20-25, Washington DC, USA
    • J. Van Sas, U. Swerts, M. Darquennes, "Towards an Effective IDD0 Test Vector Selection and Application Methodology." Proceedings of the International Test Conference' 1996, pp 511-520, October 20-25, 1996, Washington DC, USA.
    • (1996) Proceedings of the International Test Conference' 1996 , pp. 511-520
    • Sas, J.V.1    Swerts, U.2    Darquennes, M.3
  • 11
    • 0002643850 scopus 로고    scopus 로고
    • Off chip monitors and built in current sensors for analogue and mixed signal testing
    • 12-13 November, San Jose, California, USA
    • Maidon Y., Deval Y., Manhaeve H., "Off Chip Monitors and Built In Current Sensors for Analogue and Mixed Signal Testing", Proceedings of the IEEE International Workshop on IDDQ Testing IDDQ98, pp. 59-63, 12-13 November 1998, San Jose, California, USA.
    • (1998) Proceedings of the IEEE International Workshop on IDDQ Testing IDDQ98 , pp. 59-63
    • Maidon, Y.1    Deval, Y.2    Manhaeve, H.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.