Defect Coverage of Boundary-Scan Tests: What does it mean when a Boundary-Scan test passes?

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 1268-1276

  Parker, Kenneth P ^a  

^a AGILENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; DEFECTS; DESIGN FOR TESTABILITY; ELECTRIC NETWORK ANALYSIS; RESISTORS;

TEST COVERAGE;

INTEGRATED CIRCUIT TESTING;

EID: 0142246844     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. [Hird02] "Test Coverage: What Does It Mean when a Board Test Passes", K. Hird, K. P. Parker and B. Follis, Proceedings, International Test Conference, 2002, pages 1066-1074
2. rd Edition, K. P. Parker, Kluwer Academic Press, Norwell MA, 2003
3. [IEEE01] "IEEE Standard Test Access Port and Boundary-Scan Architecture", IEEE Std 1149.1-2001
4. [IEEE03] "IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks", IEEE Std 1149.6-2003
5. [IEEE99] "IEEE Standard for a Mixed-Signal Test Bus", IEEE Std 1149.4-1999
6. [Tege96] "Opens Board Test Coverage: When is 99% Really 40%", M. V. Tegethoff, K. P. Parker, K. Lee, Proceedings, International Test Conference, 1996, pages 333-339.