Improved symbolic verification using partitioning techniques

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2860, Issue , 2003, Pages 410-424

  Iyer, Subramanian ^a,b   Sahoo, Debashis ^a,c   Stangier, Christian ^a   Narayan, Amit ^a   Jain, Jawahar ^a  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

^b University of Texas at Austin   (United States)

^c Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN;

BENCHMARK CIRCUIT; INVARIANT CHECKING; LARGE DESIGNS; PARTITIONING TECHNIQUES; REACHABILITY; STATE OF THE ART; SYMBOLIC MODEL CHECKING; SYMBOLIC VERIFICATION;

MODEL CHECKING;

EID: 0142214476     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-39724-3_35     Document Type: Article

References (19)

1. Vis verilog benchmarks http://vlsi.colorado.edu/vis/. Technical report.
2. B. Bollig and I. Wegener. Partitioned bdds vs. other bdd models. In Proc. of the Intl. Workshop on Logic Synthesis, 1997.
3. R. K. Brayton, G. D. Hachtel, A. L. Sangiovanni-Vincentelli, F. Somenzi, A. Aziz, S. Cheng, S. A. Edwards, S. P. Khatri, Y. Kukimoto, A. Pardo, S. Qadeer, R. K. Ranjan, S. Sarwary, T. R. Shiple, G. Swamy, and T. Villa. VIS: A System for Verification and Synthesis. In Computer Aided Verification, 1996.
4. R. E. Bryant. Graph based algorithms for Boolean function representation. IEEE Transactions on Computers, C-35:677-690, August 1986.
5. J. R. Burch, E. M. Clarke, and D. E. Long. Symbolic Model Checking with Partitioned Transition Relations. In Proc. of the Design Automation Conf., pages 403-107, June 1991.
6. E.M. Clarke and E.A. Emerson. Design and synthesis of synchronization skeletons using branching time temporal logic. In Proc. IBM Workshop on Logics of Programs, volume 131 of Lecture Notes in Computer Science, pages 52-71. Springer-Verlag, 1981.
7. E.M. Clarke, E.A. Emerson, and A.P. Sistla. Automatic verification of finite state concurrent systems using temporal logic specifications. ACM Transactions on Programming Languages and Systems, 8:244-263, 1986.
8. O. Coudert, C. Berthet, and J. C. Madre. Verification of Sequential Machines Based on Symbolic Execution. In Proc. of the Workshop on Automatic Verification Methods for Finite State Systems, Grenoble, France, 1989.
9. Orna Grumberg, Tamir Heyman, and Assaf Schuster. Distributed symbolic model checking for μ-calculus. In Computer Aided Verification, pages 350-362, 2001.
10. Tamir Heyman, Daniel Geist, Orna Grumberg, and Assaf Schuster. Achieving scalability in parallel reachability analysis of very large circuits. In Computer Aided Verification, pages 20-35, 2000.
11. J. Jain. On analysis of boolean functions. Ph.D Dissertation, Dept. of Electrical and Computer Engineering, The University of Texas at Austin, 1993.
12. J. Jain, J. Bitner, D. S. Fussell, and J. A. Abraham. Functional partitioning for verification and related problems. Brown/MIT VLSI Conference, March 1992.
13. Kenneth L. McMillan. Symbolic Model Checking. Kluwer Academic Publishers, 1993.
14. I. Moon, G. D. Hachtel, and F. Somenzi. Border-Block Triangular Form and Conjunction Schedule in Image Computation. In Proc. of Formal Methods in CAD (FMCAD'00), volume 1954 of Lecture Notes in Computer Science, 2000.
15. A. Narayan, A. Isles, J. Jain, R. Brayton, and A. Sangiovanni-Vincentelli. Reachability Analysis Using Partitioned-ROBDDs. In Proc. of the Intl. Conf. on Computer-Aided Design, pages 388-393, 1997.
16. A. Narayan, J. Jain, M. Fujita, and A. L. Sangiovanni-Vincentelli. Partitioned-ROBDDs - A Compact, Canonical and Efficiently Manipulable Representation for Boolean Functions. In Proc. of the Intl. Conf. on Computer-Aided Design, pages 547-554, 1996.
17. R. K. Ranjan, A. Aziz, R. K. Brayton, C. Pixley, and B. Plessier. Efficient BDD Algorithms for Synthesizing and Verifying Finite State Machines. In Proc. of the Intl. Workshop on Logic Synthesis, 1995.
18. Fabio Somenzi. CUDD: CU Decision Diagram Package ftp://vlsi.colorado.edu/pub. Technical report.
19. H. J. Touati, H. Savoj, B. Lin, R. K. Brayton, and A. L. Sangiovanni-Vincentelli. Implicit State Enumeration of Finite State Machines using BDD's. In Proc. of the Intl. Conf. on Computer-Aided Design, pages 130-133, November 1990.