Achieving scalability in parallel reachability analysis of very large circuits

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1855, Issue , 2000, Pages 20-35

  Heyman, Tamir ^a   Geist, Danny ^b   Grumberg, Orna ^a   Schuster, Assaf ^a  

^a TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

^b IBM HAIFA RESEARCH LAB   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

AXIAL FLOW; COMPUTER AIDED ANALYSIS; EFFICIENCY; MEMORY ARCHITECTURE; SCALABILITY; TIMING CIRCUITS;

ADAPTIVE PARTITIONING; DISTRIBUTED MEMORY; DISTRIBUTED TERMINATION; HIGH PERFORMANCE MODELING; PARTITIONING ALGORITHMS; REACHABILITY ANALYSIS; SPACE REQUIREMENTS; SYMBOLIC REACHABILITY ANALYSIS;

MODEL CHECKING;

EID: 84944382125     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/10722167_6     Document Type: Conference Paper

References (11)

1. S. Basonov. Parallel Implementation of BDD on DSM Systems, 1998. M.Sc. thesis, Computer Science Department, Technion.
2. I. Beer, S. Ben-David, C. Eisner, and A. Landver. Rulebase: an industry-oriented formal verification tool. In 33rd Design Automation Conference, pages 655-660, 1996.
3. I. Beer, S. Ben-David, and A. Landver. On-the-fly model checking of rctl formulas. In 10th Computer Aided Verification, pages 184-194, 1998.
4. R. E. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Transactions on Computers, C-35(8):677-691, 1986.
5. Gianpiero Cabodi, Paolo Camurati, and Stefano Que. Improved reachability analy- sis of large fsm. In Proceedings of the IEEE International Conference on Computer Aided Design, pages 354-360. IEEE Computer Society Press, June 1996.
6. Olivier Coudert, Jean C. Madre, and Christian Berthet. Verifying Temporal Pro- perties of Sequential Machines Without Building their State Diagrams. In R. Kurs- han and E. M. Clarke, editors, Workshop on Computer Aided Verification, DI- MACS, pages 75-84. American Mathematical Society, Providence, RI, 1990.
7. K. L. McMillan. Symbolic Model Checking: An Approach to the State Explosion Problem. Kluwer Academic Publishers, 1993.
8. Adrian A. Narayan, Jain J. Jawahar Isles, Robert K. Brayton, and Alberto L. Sangiovanni-Vincentelli. Reachability analysis using partitioned-robdds. In Pro- ceedings of the IEEE International Conference on Computer Aided Design, pages 388-393. IEEE Computer Society Press, June 1997.
9. Adrian A. Narayan, Jain Jawahar, M. Fujita, and A. Sangiovanni-Vincentelli. Partitioned-robdds. In Proceedings of the IEEE International Conference on Com- puter Aided Design, pages 547-554. IEEE Computer Society Press, June 1996.
10. Ulrich Stern and David L. Dill. Parallelizing the murphy verifier. In Proc. of the 9th International Conference on Computer Aided Verification, LNCS 1254, pages 256-267. Springer, June 1997.
11. T. Stornetta and F. Brewer. Implementation of an efficient parallel bdd package. In Design Automation Conference. IEEE Computer Society Press, 1996.