Finfet with isolated n+ and p+ gate regions strapped with Metal and Polysilicon

IEEE International SOI Conference

Volumn , Issue , 2003, Pages 109-110

  Mathew, L ^b   Sadd, M ^b   White, B E ^b   Vandooren, A ^b   Dakshina Murthy, S ^a   Cobb, J ^b   Stephens, T ^b   Mora, R ^b   Pham, D ^b   Conner, J ^b   White, T ^b   Shi, Z ^b   Thean, A V Y ^b   Barr, A ^b   Zavala, M ^b   Schaeffer, J ^b   Rendon, M J ^b   Sing, D ^b   Orlowski, M ^b   Nguyen, B Y ^b   Mogab, J ^b   more..

^a MOTOROLA INC   (United States)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; DOPING (ADDITIVES); GATES (TRANSISTOR); OXIDATION; POLYSILICON;

DOPANT FLUCTUATIONS;

MOSFET DEVICES;

EID: 0142185867     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/soi.2003.1242918     Document Type: Conference Paper

References (6)

1. D. Hisamoto et al, IEEE TED, Vol.38, p 1419-1424,1991
2. H-S-P. Wong et al. IEDM Tech Dig., 1997 p 427-430
3. F-L Yang et al, IEDM Tech Dig., 2002, p 255-258
4. J. Kedzierski et al, IEDM 2001, p 437-440
5. J. Kedzierski et al, IEDM 2002, p 247-250
6. A. Thean et al, IEEE 2002 Silicon Nanoelect. Work., p 25