Challenges of back end of the line for sub 65 nm generation

Microelectronic Engineering

Volumn 70, Issue 2-4, 2003, Pages 255-266

  Fayolle, M ^a   Passemard, G ^b   Louveau, O ^b   Fusalba, F ^b   Cluzel, J ^a  

^a CEA GRENOBLE   (France)

^b STMICROELECTRONICS   (France)

Author keywords

45 nm node; 65 nm node; Integration; Interconnect; Porous dielectric; Reliability; Size effect; Ultra low K dielectric

Indexed keywords

PERMITTIVITY; POROSITY;

POROUS DIELECTRIC;

DIELECTRIC MATERIALS;

EID: 0142106901     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(03)00467-2     Document Type: Conference Paper

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