An on-chip self-repair calculation and fusing methodology

IEEE Design and Test of Computers

Volumn 20, Issue 5, 2003, Pages 67-75

  Anand, Darren ^a   Cowan, Bruce ^a   Farnsworth, Owen ^a   Jakobsen, Peter ^a   Oakland, Steve ^a   Ouellette, Michael R ^a   Wheater, Donald L ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUILT-IN SELF TEST; CALCULATIONS; DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC FUSES; FIELD EFFECT TRANSISTORS; INTERFACES (COMPUTER); LASER APPLICATIONS; POLYSILICON; SHIFT REGISTERS; STATIC RANDOM ACCESS STORAGE;

ELECTRICALLY PROGRAMMABLE POLYSILICON FUSE; FUSE LATCH; LASER FUSING METHOD; PROGRAMMABLE SHIFT REGISTER;

INTEGRATED CIRCUIT TESTING;

EID: 0142103279     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2003.1232258     Document Type: Article

References (6)

1. M. Ouelette, D. Anand, and P. Jakobsen, "Shared Fuse Macro for Multiple Embedded Memory Devices with Redundancy," Proc. IEEE Custom Integrated Circuits Conf. (CICC 01), IEEE Press, 2001, pp. 191-194.
2. J. Dreibelbis et al., "Processor-Based Built-in Self-Test for Embedded DRAM," IEEE J. Solid-State Circuits, vol. 33, no. 11, Nov. 1998, pp. 1731-1740.
3. N. Watanabe et al., "An Embedded DRAM Hybrid Macro with Auto Signal Management and Enhanced-on-Chip Tester," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 01), IEEE Press, 2001, pp. 388-389, 469.
4. B. Cowan et al., "On-Chip Repair and an ATE Independent Fusing Methodology," Proc. IEEE Int'l Test Conf. (ITC 02), IEEE Press, Oct. 2002, pp. 178-186.
5. C. Kothandaraman et al., "Optimisation of CoSi2 Based Electrical Fuses for Redundancy Implementation in Sub-0.13μm Embedded DRAM Applications," Proc. Int'l Conf. Solid State Devices and Materials (SSDM 00), Japan Soc. of Applied Physics, 2000, pp. 166-167.
6. V. Klee et al., "A 0.13 μm Logic-Based Embedded DRAM Technology with Electrical Fuses, Cu Interconnect in SiLK, Sub-7ns Random Access Time and Its Extension to the 0.10 μm Generation," Proc. Int'l Electron Device Meeting, IEEE Press, 2001, pp. 407-410.