Pipelined Delay-Sum Architecture Based on Bucket-Brigade Devices for On-Chip Ultrasound Beamforming

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 10, 2003, Pages 1754-1757

  Mo, Yaowu ^a   Tanaka, Tsunehisa ^a   Arita, Shigeru ^a   Tsuchitani, Akira ^a   Inoue, Koji ^a   Suzuki, Yoshihiko ^a,b  

^a OSAKA MUNICIPAL TECHNICAL RESEARCH INSTITUTE   (Japan)

^b IEEE   (United States)

Author keywords

Beamforming; Delay lines; Image sensors; Phased arrays; Ultrasonic devices

Indexed keywords

AMPLIFIERS (ELECTRONIC); ARRAYS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); HARMONIC DISTORTION; IMAGE SENSORS; MICROMACHINING; PIEZOELECTRIC DEVICES; SUMMING CIRCUITS; ULTRASONIC DEVICES;

ULTRASOUND BEAMFORMING;

ELECTRIC DELAY LINES;

EID: 0141920406     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.817603     Document Type: Article

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