Increasing the Immunity to Electromagnetic Interferences of CMOS OpAmps

IEEE Transactions on Reliability

Volumn 52, Issue 3, 2003, Pages 349-353

  Richelli, Anna ^a   Colalongo, Luigi ^a   Kovács Vajna, Zsolt M ^a  

^a UNIVERSITY OF BRESCIA   (Italy)

Author keywords

CMOS; Electromagnetic interferences; Operational amplifier; Parasitic effect; Slew rate; Symmetric topology

Indexed keywords

COMPUTER SIMULATION; ELECTRIC LOADS; ELECTRIC POTENTIAL; GAIN CONTROL; INTERFERENCE SUPPRESSION; OPERATIONAL AMPLIFIERS; SIGNAL INTERFERENCE;

PARASITIC EFFECT; POWER PINS; SLEW RATES;

CMOS INTEGRATED CIRCUITS;

EID: 0141898418     PISSN: 00189529     EISSN: None     Source Type: Journal    
DOI: 10.1109/TR.2003.817847     Document Type: Article

References (6)

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3. G. Masetti, S. Graffi, D. Golzio, and Z. M. Kovács-Vajna, "Failures induced on analog integrated circuits from conveyed electromagnetic interferences: A review," Microelectronics and Reliability, vol. 36, no. 7/8, pp. 995-972, 1996.
4. G. Setti and N. Speciale, "Design of a low EMI susceptibility CMOS operational amplifier," Microelectronics and Reliability, vol. 38, p. 1143, 1998.
5. G. Masetti, G. Setti, and N. Speciale, "On the key role of parasitic capacitances in the determination of susceptibility to EMI of integrated operational amplifiers," in Proc. EMC1999 Zurich, 1999.
6. Z. M. Kovács-Vajna, E. Sardini, and N. Speciale, "Chaotic behavior of 741 OpAmps subjected to EMI conveyed to power supply rails." in Proc. ISCAS2000 Geneva, vol. 1, May 2000, pp. 727-730.