Line-edge roughness reduction and CD slimming using hardbake processing

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5038 II, Issue , 2003, Pages 1131-1142

  Peters, Richie ^a   Lucas, Kevin ^a   Cobb, Jonathan ^a   Parker, Colita ^a   Patterson, Kyle ^b   McCauley, Robb ^a   Ercken, Monique ^c   Van Roey, Frieda ^c   Vandenbroeck, Nadia ^c   Pollentier, Ivan ^c  

^a MOTOROLA INC   (United States)

^b MOTOROLA INC   (United States)

^c IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

PHOTOLITHOGRAPHY; PHOTORESISTS; PROCESS CONTROL; SHRINKAGE; SPATIAL VARIABLES CONTROL; SURFACE ROUGHNESS;

CHEMICALLY AMPLIFIED RESISTS; CRITICAL DIMENSION SLIMMING; HARDBAKE PROCESSING; LINE EDGE ROUGHNESS REDUCTION;

TRANSISTORS;

EID: 0141834896     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.485027     Document Type: Conference Paper

References (5)

1. http://www.itrs.net/public.
2. I. Pollentier, P. Jaenen, C. Baerts, K. Ronse. Sub-50nm gate patterning using CD trim techniques and 248nm or 193nm lithography. Proc. of ARCH Interface 2001.
3. K. Ronse, et. al. Proc. of SPIE Vol. 4000, pp410-422, 2000.
4. K. Lucas, M. Slezak, M. Ercken, F. Van Roey, '193nm contact photoresist reflow feasibility study', Proc. of SPIE, Vol. 4345 (2001).
5. Personal communication Makoto Shimizu, February, 2003.