Line edge roughness reduction for advanced metal gate etch with 193nm lithography in a silicon decoupled plasma source etcher (DPSII)

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5039 I, Issue , 2003, Pages 240-248

  Chowdhury, Tito ^a   Bamnolker, Hanna ^a   Khen, Roni ^a   Yang, Chan Lon ^a   Lee, Hean Cheal ^a   Du, Yan ^b   Shen, Meihua ^b   Choi, Jinhan ^b   Deshmukh, Shashank ^b  

^a CYPRESS SEMICONDUCTOR   (United States)

^b APPLIED MATERIALS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DRY ETCHING; MASKS; NITRIDES; PLASMA ETCHING; PLASMA SOURCES; SEMICONDUCTING SILICON; SURFACE ROUGHNESS; THICKNESS MEASUREMENT;

ADVANCED METAL GATE ETCH; DECOUPLED PLASMA ETCHER; LINE EDGE ROUGHNESS;

LITHOGRAPHY;

EID: 0141834795     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.485151     Document Type: Conference Paper

References (2)

1. T. Miyamoto et al, J. Vac.Sci.Technol. B 9(2), Mar/Apr 1991
2. An Experimentally Validated Analytical Model For Gate Line Edge Roughness (LER) Effects on Technology Scaling", Diaz IEEE Electron Device Letters Vol. 22 No.6 June 2001