Modeling and Simulation of 12.5 Gb/s on a HyperBGA® Package

Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium

Volumn , Issue , 2003, Pages 143-147

  McBride, Ryan D ^a   Rosser, Steven G ^a   Nowak, Ronald P ^a  

^a Endicott Interconnect Technologies Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDARY CONDITIONS; COMPUTER SIMULATION; COMPUTER SOFTWARE; MICROPROCESSOR CHIPS; APPLICATION PROGRAMS; CROSSTALK; DISTORTION (WAVES); ELECTRIC IMPEDANCE; INDUSTRIAL ELECTRONICS; INSERTION LOSSES; JITTER; MANUFACTURE; PACKAGING;

DIFFERENTIAL SIGNALING;

ELECTRONICS PACKAGING; COMPUTER SOFTWARE;

FREQUENCY; INTERCONNECT TECHNOLOGY; MODEL AND SIMULATION; PERFORMANCE REQUIREMENTS; PHYSICAL STRUCTURES; PROPAGATION LOSS; ROUTING; SIGNAL DESIGN;

EID: 0141676785     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. D. J. Alcoe, et al, "A High Performance, Low Stress, Laminate Ball Grid Array Flip Chip Carrier," Semiconductor Packaging Technologies Symposium, SEMICON WEST 99, San Jose, CA, July 1999.
2. Maxim Integrated Products, Sunnyvale, CA, "Jitter Specifications Made Easy", Application Note: HFAN-4.3.0, Rev-0, February, 2001, http://pdfserv.maximic.com/arpdf/AppNotes/10_an430.pdf
3. S. Seat, "An eye-opening look at jitter", EDN Magazine, October 17, 2002, pg 75.
4. st Electronics Components and Technology Conference, Session 31, Paper 1, May, 2001.