A Novel Approach for Integration of Dual Metal Gate Process Using Ultra Thin Aluminum Nitride Buffer Layer

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2003, Pages 149-150

  Park, Chang Seo ^a   Cho, Byung Jin ^a   Yan, Du An ^b   Balasubramanian, N ^b   Kwong, Dim Lee ^c  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

^c The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALUMINUM NITRIDE; ANNEALING; INTERFACES (MATERIALS); SPUTTERING; CMOS INTEGRATED CIRCUITS; ETCHING; GATE DIELECTRICS; METALS; NITRIDES; WORK FUNCTION;

GATE METALS;

CMOS INTEGRATED CIRCUITS; BUFFER LAYERS;

DUAL METAL GATE; ETCHING PROCESS; EXPOSED TO; GATE OXIDE; GATE PROCESS; METAL ETCHING; METAL-DIELECTRIC INTERFACE; METAL-GATE; PROCESSES INTEGRATIONS; ULTRA-THIN;

EID: 0141649547     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. D. -G. Park et al, IEDM Tech. Dig., p. 671, 2001.
2. J. H. Lee et al, IEDM Tech. Dig., p.359, 2002.
3. I. Polishchuk et al, Electron Device Letters, vol.23, p.200, 2002.
4. R. Lin et al, Electron Device Letters, vol.23, p.49, 2002.
5. Y. -K. Choi et al, IEDM Tech. Dig., p.259, 2002.