Integrated Pulse Neuron Circuit for Asynchronous Pulse Neural Networks

Proceedings of the International Joint Conference on Neural Networks

Volumn 2, Issue , 2003, Pages 942-947

  Taniguchi, Takuya ^a   Horio, Yoshihiko ^a   Aihara, Kazuyuki ^b  

^a TOKYO DENKI UNIVERSITY   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ENCODING (SYMBOLS); INTEGRATED CIRCUIT LAYOUT; PULSE WIDTH MODULATION;

PULSE NEURON CIRCUITS;

NEURAL NETWORKS;

EID: 0141572360     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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