Asynchronous pulse neural network model for VLSI implementation

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E81-A, Issue 9, 1998, Pages 1853-1859

  Hanagata, Mitsuru ^a   Horio, Yoshihiko ^a   Aihara, Kazuyuki ^b,c  

^a TOKYO DENKI UNIVERSITY   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

^c JAPAN SCIENCE AND TECHNOLOGY AGENCY   (Japan)

Author keywords

Dynamical cell assembly; Neural networks; Spatio temporal coding

Indexed keywords

ENCODING (SYMBOLS); VLSI CIRCUITS;

DYNAMICAL CELL ASSEMBLY; SPATIOTEMPORAL CODING;

NEURAL NETWORKS;

EID: 0032156012     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (14)

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