Efficient interleaver memory architectures for serial turbo decoding

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 2, Issue , 2003, Pages 629-632

  Wang, Zhongfeng ^a   Parhi, Keshab ^b  

^a NATIONAL SEMICONDUCTOR CORPORATION   (United States)

^b NONE

Author keywords

Interleaver; Low complexity; Memory; Serial architecture; Turbo code

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; DECODING; PROBABILITY; TURBO CODES;

INTERLEAVER MEMORY ARCHITECTURES;

CODE DIVISION MULTIPLE ACCESS;

EID: 0141496198     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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