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Volumn 2, Issue , 2003, Pages 977-982

A VLSI Hamming Artificial Neural Network with k-Winner-Take-All and k-Loser-Take-All Capability

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE; COMPUTER SIMULATION; COMPUTER SOFTWARE; EMBEDDED SYSTEMS; IMAGE PROCESSING; VLSI CIRCUITS;

EID: 0141460611     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (8)

References (10)
  • 1
    • 0141708889 scopus 로고    scopus 로고
    • Digital IC Implementations
    • E. Fiesler, R. Beale, Edts. Oxford University Publishing
    • V. Beiu, Digital IC Implementations, Handbook of Neural Computation, E. Fiesler, R. Beale, Edts. Oxford University Publishing, 1997.
    • (1997) Handbook of Neural Computation
    • Beiu, V.1
  • 2
    • 0141708888 scopus 로고    scopus 로고
    • Analog VLSI Implementation of Neural Networks
    • E. Fiesler, R. Beale, Edts. Oxford University Publishing
    • E. A. Vittoz, Analog VLSI Implementation of Neural Networks, Handbook of Neural Computation, E. Fiesler, R. Beale, Edts. Oxford University Publishing, 1997.
    • (1997) Handbook of Neural Computation
    • Vittoz, E.A.1
  • 3
    • 0023331258 scopus 로고
    • An Introduction to Computing with Neural Nets
    • April
    • R. P. Lippmann, An Introduction to Computing with Neural Nets, IEEE ASSP Magazing, April 1987.
    • (1987) IEEE ASSP Magazing
    • Lippmann, R.P.1
  • 4
  • 6
    • 0033280259 scopus 로고    scopus 로고
    • Mixed analogue-digital artificial neural network architecture with on-chip learning
    • December
    • A. Schmid, Y. Leblebici, D. Mlynek, Mixed analogue-digital artificial neural network architecture with on-chip learning, IEE Proc. Circ. Dev. and Syst., Vol. 146, No. 6, December 1999.
    • (1999) IEE Proc. Circ. Dev. and Syst. , vol.146 , Issue.6
    • Schmid, A.1    Leblebici, Y.2    Mlynek, D.3
  • 8
    • 0031628743 scopus 로고    scopus 로고
    • Modular Realization of Threshold Logic Gates for High-Performance Digital Signal Processing Applications
    • Y. Leblebici, F. K. Gurkaynak, Modular Realization of Threshold Logic Gates for High-Performance Digital Signal Processing Applications, IEEE ASIC Conference, 1998.
    • (1998) IEEE ASIC Conference
    • Leblebici, Y.1    Gurkaynak, F.K.2
  • 9
    • 0033331433 scopus 로고    scopus 로고
    • A Two-Stage Charge-Based Analog/Digital Neuron Circuit with Adjustable Weights
    • A. Schmid, Y. Leblebici, D. Mlynek, A Two-Stage Charge-Based Analog/Digital Neuron Circuit with Adjustable Weights, IJCNN, 1999.
    • (1999) IJCNN
    • Schmid, A.1    Leblebici, Y.2    Mlynek, D.3
  • 10
    • 0141708886 scopus 로고    scopus 로고
    • VLSI Realization of a Two-Dimensional Hamming Distance Comparator ANN for Image Processing Applications
    • S. Badel, A. Schmid, Y. Leblebici, VLSI Realization of a Two-Dimensional Hamming Distance Comparator ANN for Image Processing Applications, ESANN, 2003.
    • (2003) ESANN
    • Badel, S.1    Schmid, A.2    Leblebici, Y.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.