Strained FIP-SOI (FinFET/FD/PD-SOI) for Sub-65 nm CMOS Scaling

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2003, Pages 137-138

  Yang, Fu Liang ^a   Chen, Hou Yu ^a   Huang, Chien Chao ^a   Ge, Chun Hu ^a   Su, Ke Wei ^a   Huang, Cheng Chuan ^a   Chang, Chang Yun ^a   Lin, Da Wen ^a   Wu, Chung Cheng ^a   Ho, Jaw Kang ^a   Lee, Wen Chin ^a   Yeo, Yee Chia ^a   Diaz, Carlos H ^a   Liang, Mong Song ^a   Sun, Jack Y C ^a   Hu, Chenming ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC RESISTANCE; MICROPROCESSOR CHIPS; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES; TRANSMISSION ELECTRON MICROSCOPY; MOS DEVICES;

SHALLOW TRENCH ISOLATION (STI);

FIELD EFFECT TRANSISTORS; FINFET;

65-NM DEVICES; ADDITIONAL STRUCTURES; CMOS SCALING; DEVICE-SCALING; FEATURE SIZES; PERFORMANCE GAIN; SIZE-SCALING; SOI TECHNOLOGY; STRAINED-SILICON; STRAINED-SOI;

EID: 0141426799     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. G. Q. Shahidi, IBM J. Res. Dev., vol. 46, pp. 121, 2002.
2. K. Nowka et al., ISSCC 2002, pp. 340.
3. M. Celik et al., VLSI Symp. 2002, pp. 166.
4. Y. W. Kim et al., IEDM 2002, pp. 69.
5. M. Khare et al., IEDM 2002, pp. 407.
6. A. Shimizu-et al., IEDM 2001, pp. 433.
7. S. Thompson et al., IEDM 2002, pp. 61.
8. B.H. Lee et al., IEDM 2002, pp. 946.