The IBM ASIC/SoC methodology-A recipe for first-time success

IBM Journal of Research and Development

Volumn 46, Issue 6, 2002, Pages 649-660

  Doerre, G W ^a   Lackey, D E ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; MICROPROCESSOR CHIPS; NANOTECHNOLOGY;

IBM MICROELECTRONICS (CO); PRODUCT INTEGRATION; SYSTEM-ON-A-CHIP (SOC); TURNAROUND TIME (TAT);

INTEGRATED CIRCUIT LAYOUT;

EID: 0043194361     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.466.0649     Document Type: Article

References (31)

1. Cadence® "AMS Designer," ©2002 Cadence Design Systems, Inc.; see http://www.cadence.com/products/amsdesigner.html.
2. "Design Process Automation," © 2001 Interweave Tech Corporation; see http://www.interweavetech.com/.
3. Get2Chip®, "Get2Chip and Prolific Liquid Cell Study," © 2001 Get2Chip.com, Inc.; see http://www.get2chip.com/docs/white_papers/ g2c-lci.asp.
4. eSilicon®, "eSilicon Access," ©2001 eSilicon Corporation; see http://www.esilicon.com/services/access.html.
5. Artisan Components®, "Process-Perfect Products," © 2001 Artisan Components, Inc.; see http://www.artisan.com/products.
6. IEEE Standard 1076-1993, "IEEE Standard VHDL Language Reference Manual," © 1998-1999 IEEE; see http://standards.ieee.org/reading/ieee/ std_public/description/dasc/1076-1993_desc.html.
7. IEEE Standard 1364-1995, "IEEE Standard Hardware Description Language Based on the Verilog® Hardware Description Language," © 1998-1999 IEEE; see http://standards.ieee.org/reading/ieee/std_public/ description/dasc/1364-1995_desc.html.
8. "Memory Arrays in IBM ASICs," IBM Application Note, © 2001 International Business Machines; see http://w3asics.btv.ibm.com/.
9. J. Czilli and A. Nordstrom, "Synthesizing a 650K Gate Deep Submicron ASIC," presented at the 1997 Synopsys Users Group (SNUG '97), San Jose; see http://www.snug-universal.org.
10. J. J. Engel, T. S. Guzowski, A. Hunt, D. E. Lackey, L. D. Pickup, R. A. Proctor, K. Reynolds, A. M. Rincon, and D. R. Stauffer, "Design Methodology for IBM ASIC Products," IBM J. Res. & Dev. 40, No. 4, 387-406 (July 1996).
11. S. Oakland, J. Monzel, R. Bassett, and P. Gillis, "An ASIC Foundry View of Design for Test," Proceedings of the IEEE International Test Conference, 1994, Test Synthesis Seminar addendum, paper 4.2.
12. V. Chickermane, B. Koenemann, T. Guzowski, T. W. Williams, A. Sullivan, and S. Oakland, "DFT: Test Synthesis and Beyond," Proceedings of the IEEE International Test Conference, 1994, Test Synthesis Seminar addendum, paper 3.3.
13. S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, "Optimization by Simulated Annealing," Science 220, No. 4598 (1983).
14. J. Vygen, "Algorithms for Large-Scale Flat Placement," Proceedings of the 34th Design Automation Conference, 1997, pp. 746-751.
15. G. L. Smith, R. J. Bahnsen, and H. Halliwell, "Boolean Comparison of Hardware and Flowcharts," IBM J. Res. & Dev. 26, No. 1, 106-116 (January 1982).
16. G. E. Moore, "Cramming More Components onto Integrated Circuits," Electronics 38, No. 8, 114-117 (1965).
17. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley Publishing Co., Reading, MA, 1990.
18. D. Lackey, "Applying Placement-Based Synthesis for On-Time System-on-a-Chip Design," IEEE Custom Integrated Circuits Conference, 2000, pp. 121-124.
19. Cadence® "Physically Knowledgeable Synthesis," © 2002 Cadence Design Systems, Inc.; see http://www.cadence.com/products/pks.html.
20. Synopsys© "Unified Synthesis and Placement," © 2002 Synopsys, Inc.; see http://www.synopsys.com/products/unified_synthesis/ unified_synthesis.html.
21. J. Darringer, E. Davidson, D. J. Hathaway, B. Koenemann, M. Lavin, J. K. Morrell, K. Rahmat, W. Roesner, E. Schanzenbach, G. Tellez, and L. Trevillyan, "EDA in IBM, Past, Present and Future," IEEE Trans. Computer Aided Design 19, No. 12, 1476-1497 (December 2000).
22. A. Hetzel, "A Sequential Detailed Router for Huge Grid Graphs. Design, Automation, and Test in Europe," Proceedings of the IEEE International Conference on Computer Aided Design, 1996, pp. 332-338.
23. C. Albrecht, B. Korte, J. Schietke, and J. Vygen, "Cycle Time and Slack Optimization for VLSI Chips," Proceedings of the IEEE International Conference on Computer Aided Design, 1999, pp. 232-238.
24. M. Kuzawinski, "High-Density Package Applications for Wire Bond and Flip Chip," Proceedings of the Semiconductor Packaging Technologies Symposium - SEMICON West '99, 1999.
25. IEEE Standard 1149.1-1990, "IEEE Standard Test Access Port and Boundary-Scan Architecture," © 1998-1999 IEEE; see http://standards.ieee.org/reading/ieee/std_public/description/testtech/1149. 1-1990_desc.html.
26. V. Chickermane, D. Lackey, D. Litten, and L. Smudde, "Automated Chip-Level I/O and Test Insertion Using IBM Design-for-Test Synthesis," IBM Micronews 6, No. 2, 18-22 (Second Quarter 2000).
27. D. Lackey and J. Morrell, "Interoperability, an IBM Perspective," IBM Microelectronics Division 2001, presentation at the 2001 Design Automation Conference Interoperability Workshop.
28. IEEE Standard 1481-1999, "Integrated Circuit (IC) Delay and Power Calculation System," © 1999 IEEE; see http://standards.ieee.org/ reading/ieee/std/dasc/1481-1999.pdf.
29. D. Lackey, "Design Planning Methodology for Rapid Chip Deployment," Proceedings of the Eighth IEEE/DATC Electronics Design Processes Workshop (EDP 2001), pp. 111-116.
30. A. Dean, D. Garrett, M. Stan, and S. Ventrone, "Low Power Design for ASIC Cores," VLSI Design, pp. 1-15 (2000).
31. P. Bardell and W. McAnney, "Self-Testing of Multiple Chip Modules," Proceedings of the IEEE International Test Conference, 1982, pp. 200-204.