Automatic trace analysis for logic of constraints

Proceedings - Design Automation Conference

Volumn , Issue , 2003, Pages 460-465

  Chen, Xi ^a   Hsieh, Harry ^a   Balarin, Felice ^b   Watanabe, Yosinori ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

Author keywords

Logic of Constraints; Performance constraint; Simulation checker; Trace analysis

Indexed keywords

COMPUTER SIMULATION; DIGITAL SIGNAL PROCESSING; MICROPROCESSOR CHIPS; PRODUCT DESIGN;

AUTOMATIC TRACE ANALYSIS;

EMBEDDED SYSTEMS;

EID: 0043136668     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/775949.775952     Document Type: Conference Paper

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