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Volumn 8, Issue 3, 2003, Pages 316-333

Congestion reduction during placement with provably good approximation bound

Author keywords

Congestion; Physical design; Placement; Routability

Indexed keywords

ALGORITHMS; APPROXIMATION THEORY; COMPUTATIONAL COMPLEXITY; DESIGN AIDS; INTEGER PROGRAMMING; INTEGRATED CIRCUIT LAYOUT; LINEAR PROGRAMMING;

EID: 0042745487     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/785411.785414     Document Type: Article
Times cited : (11)

References (17)
  • 3
    • 0031645537 scopus 로고    scopus 로고
    • Performance driven multi-layer general area routing for PCB/MCM designs
    • Cong, J. and Madden, P. 1998. "Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs." In Design Automation Conference, pages 356-361.
    • (1998) Design Automation Conference , pp. 356-361
    • Cong, J.1    Madden, P.2
  • 4
    • 0021784846 scopus 로고
    • A procedure for placement of standard cell VLSI circuits
    • Dunlop, A. E. and Kernighan, B. W. 1985. "A Procedure for Placement of Standard Cell VLSI Circuits." IEEE Trans. Comput. Aided Design, 4, 1, 92-98.
    • (1985) IEEE Trans. Comput. Aided Design , vol.4 , Issue.1 , pp. 92-98
    • Dunlop, A.E.1    Kernighan, B.W.2
  • 5
    • 0010311574 scopus 로고    scopus 로고
    • IBM-Place benchmark
    • ERLAB(a)
    • ERLAB(a). "IBM-Place benchmark." http://er.cs.ucla.edu/benchmarks/ibm-place/.
  • 6
    • 84923071212 scopus 로고    scopus 로고
    • Labyrinth
    • ERLAB(b)
    • ERLAB(b). "Labyrinth." http://www.cs.ucla.edu/~kastner/labyrinth/.
  • 12
    • 0029264395 scopus 로고
    • Efficient and effective placement for very large circuits
    • Sun, W. J. and Sechen, C. 1995. "Efficient and Effective Placement for Very Large Circuits." IEEE Trans. Comput. Aided Des. 14, 3, 349-359.
    • (1995) IEEE Trans. Comput. Aided Des. , vol.14 , Issue.3 , pp. 349-359
    • Sun, W.J.1    Sechen, C.2
  • 13
    • 0002783724 scopus 로고
    • Early wirability checking and 2-D congestion-driven circuit placement
    • Tsay, R. S. and Chang, S. C. 1992. "Early Wirability Checking and 2-D Congestion-Driven Circuit Placement." In International Conference on ASIC. pages 50-53.
    • (1992) International Conference on ASIC , pp. 50-53
    • Tsay, R.S.1    Chang, S.C.2
  • 15
    • 0034296451 scopus 로고    scopus 로고
    • Congestion minimization during top-down placement
    • Wang, M., Yang, X., and Sarrafzadeh, M. 2000b. "Congestion Minimization During Top-Down Placement." IEEE Trans. Comput. Aided Des. 19, 10, 1140-1148.
    • (2000) IEEE Trans. Comput. Aided Des. , vol.19 , Issue.10 , pp. 1140-1148
    • Wang, M.1    Yang, X.2    Sarrafzadeh, M.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.