A timing-accurate modeling and simulation environment for networked embedded systems

Proceedings - Design Automation Conference

Volumn , Issue , 2003, Pages 42-47

  Fummi, Franco ^a   Gallo, Paolo ^b   Martini, Stefano ^a   Perbellini, Giovanni ^a   Poncino, Massimo ^a   Ricciato, Fabio ^b  

^a UNIVERSITY OF VERONA   (Italy)

^b TELECOM ITALIA   (Italy)

Author keywords

Co Simulation; Emulation; Remote Debugging; SystemC

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER DEBUGGING; COMPUTER SIMULATION; DIGITAL COMMUNICATION SYSTEMS; EMBEDDED SYSTEMS; RELIABILITY; TIMING CIRCUITS;

EMULATION;

SYSTEMS ANALYSIS;

EID: 0042591352     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/775844.775846     Document Type: Conference Paper

References (11)

1. International Technology Roadmap for Semiconductor 2001. http://public.itrs.net/Files/2001ITRS/Home.htm
2. J. Muttersbach, T. Villiger, H. Kaeslin, N. Felber, W. Fichtner. "Globally-Asynchronous Locally Synchronous Architectures to Simplify the Design of On-Chip Systems", ASIC/SOC'99, pp. 317-321, 1999.
3. L. Benini, G. De Micheli. "Networks on chip: A New SoC Paradigm", IEEE Computer, Vol. 35, No. 1, pp. 70-78, Jan. 2002.
4. Synopsys Inc. SystemC User's Guide. Version 2.1, 2002.
5. L. Breslau et al. "Advances in Network Simulation," IEEE Computer, Vol. 33, No. 5, pp. 59-67, May 2000.
6. ANSI/IEEE Standard 802.11. Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications. 1999.
7. G. Nicolescu, S. Yoo, A. A. Jerraya. "Mixed-Level Cosimulation for Fine Gradual Refinement of Communication in SoC Design," DATE'01, pp. 754-759, 2001.
8. A. Chatelain, Y. Mathys, G. Placido, A. La Rosa, L. Lavagno. "High-Level Architectural Co-Simulation Using Esterel and C," CODES'01, pp. 189-194, 2001.
9. V. Aue, J. Kneip, M. Weiss, M. Bolle, G. Fettweis. "Matlab Based Co-Design Framework for Wirelss Broadband Communication DSPs," ASSP'01, Vol. 2, pp. 1253-1256.
10. D. Desmet, M. Esvelt, P. Avasare, D. Verkest, H. De Man. "Timed Executable System Specification of an ADSL Modem Using a C++ Based Design Environment: a Case Study," CODES'99, pp. 38-42, 1999.
11. R. Pasko, R. Cmar, P. Schaumont, S. Vernalde. "Functional Verification of an Embedded Network Component by Co-Simulation with a Real Network," HLDVT'00, pp. 64-67, 2000.