-
1
-
-
0042476471
-
Architectural and implementation challenges in designing high-performance RSFQ processors: A Flux-1 microprocessor and beyond
-
submitted for publication
-
M. Dorojevets and P. Bunyk, "Architectural and implementation challenges in designing high-performance RSFQ processors: A Flux-1 microprocessor and beyond," IEEE Trans. Appl. Supercond., submitted for publication.
-
IEEE Trans. Appl. Supercond.
-
-
Dorojevets, M.1
Bunyk, P.2
-
2
-
-
0041778334
-
Flux-1 RSFQ microprocessor: Physical design and test results
-
submitted for publication
-
P. Bunyk, M. Leung, and M. Dorojevets, "Flux-1 RSFQ microprocessor: Physical design and test results," IEEE Trans. Appl. Supercond., submitted for publication.
-
IEEE Trans. Appl. Supercond.
-
-
Bunyk, P.1
Leung, M.2
Dorojevets, M.3
-
3
-
-
0024629196
-
DC voltage multipliers: A novel application of synchronization in Josephson junction arrays
-
March
-
V. K. Semenov and M. A. Voronova, "DC voltage multipliers: A novel application of synchronization in Josephson junction arrays," IEEE Trans. Magn., vol. 25, pp. 1432-1435, March 1989.
-
(1989)
IEEE Trans. Magn.
, vol.25
, pp. 1432-1435
-
-
Semenov, V.K.1
Voronova, M.A.2
-
4
-
-
0035268503
-
Circuit improvements for a voltage multiplier
-
March
-
V. K. Semenov and, Yu. A. Polyakov, "Circuit improvements for a voltage multiplier," IEEE Trans. Appl. Supercond., vol. 11, pp. 550-553, March 2001.
-
(2001)
IEEE Trans. Appl. Supercond.
, vol.11
, pp. 550-553
-
-
Semenov, V.K.1
Polyakov, Yu.A.2
-
5
-
-
68649123400
-
High speed data link between digital superconductor chips
-
Apr.
-
Q. Herr, M. Wire, and A. Smith, "High speed data link between digital superconductor chips," Apl. Phys. Lett., vol. 80, pp. 3210-3212, Apr. 2002.
-
(2002)
Apl. Phys. Lett.
, vol.80
, pp. 3210-3212
-
-
Herr, Q.1
Wire, M.2
Smith, A.3
-
6
-
-
0043008084
-
-
FastHenry-2.0S and subsequent versions are provided courtesy of Whiteley Research, Inc.
-
FastHenry-2.0S and subsequent versions are provided courtesy of Whiteley Research, Inc.
-
-
-
-
7
-
-
0018916549
-
Planar coupling scheme for ultra-low noise DC SQUIDs
-
Jan.
-
J. M. Jaycox and M. B. Ketchen, "Planar coupling scheme for ultra-low noise DC SQUIDs," IEEE Trans. Appl. Mag., vol. MAG-17, Jan. 1981.
-
(1981)
IEEE Trans. Appl. Mag.
, vol.MAG-17
-
-
Jaycox, J.M.1
Ketchen, M.B.2
-
8
-
-
0041440029
-
Ballistic SFQ signal propagation on-chip and chip-to-chip
-
submitted for publication
-
Q. Herr, M. Wire, and A. Smith, "Ballistic SFQ signal propagation on-chip and chip-to-chip," IEEE Trans. Appl. Supercond., submitted for publication.
-
IEEE Trans. Appl. Supercond.
-
-
Herr, Q.1
Wire, M.2
Smith, A.3
-
9
-
-
0035269133
-
2 Nb integrated circuit process
-
Mar.
-
2 Nb integrated circuit process," IEEE Trans. Appl. Supercond., vol. 11, pp. 1061-1065, Mar. 2001.
-
(2001)
IEEE Trans. Appl. Supercond.
, vol.11
, pp. 1061-1065
-
-
Kerber, G.1
Abelson, L.2
Leung, M.3
Herr, Q.4
Johnson, M.W.5
-
10
-
-
0042944201
-
Fabrication of high current density Nb integrated circuits using a self-aligned junction anodization process
-
submitted for publication
-
G. Kerber, L. Abelson, K. Edwards, R. Hu, M. W. Johnson, M. Leung, and J. Luine, "Fabrication of high current density Nb integrated circuits using a self-aligned junction anodization process," IEEE Trans. Appl. Supercond., submitted for publication.
-
IEEE Trans. Appl. Supercond.
-
-
Kerber, G.1
Abelson, L.2
Edwards, K.3
Hu, R.4
Johnson, M.W.5
Leung, M.6
Luine, J.7
|