Implementation of phase-mode arithmetic elements for parallel signal processing

IEEE Transactions on Applied Superconductivity

Volumn 13, Issue 2 I, 2003, Pages 583-586

  Onomi, Takeshi ^a   Horima, Yohei ^a   Kobori, Masayuki ^a   Shimizu, Itsuhei ^a   Nakajima, Koji ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

Logic circuit; Phase mode; Signal processing; Single flux quantum; Superconductive device

Indexed keywords

COMPUTER SIMULATION; LOGIC CIRCUITS; MULTIPLYING CIRCUITS; PARALLEL PROCESSING SYSTEMS; SEMICONDUCTOR JUNCTIONS;

PARALLEL SIGNAL PROCESSING;

DIGITAL SIGNAL PROCESSING;

EID: 0042442209     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/TASC.2003.813952     Document Type: Conference Paper

References (9)

1. K. Nakajima, H. Mizusawa, H. Sugahara, and Y. Sawada, "Phase-mode Josephson computer system," IEEE Trans. Appl. Superconduct., vol. 1, pp. 29-36, March 1991.
2. K. K. Likharev and V. K. Semenov, "RSFQ logic/memory family: A new Josephson-junction technology for sub-terahertz-clock-frequency digital systems," IEEE Trans. Appl. Superconduct., vol. 1, pp. 3-28, March 1991.
3. K. Nakajima, G. Oya, and Y. Sawada, "Fluxoid motion in phase mode Josephson switching system," IEEE Trans. Magn., vol. MAG-19, pp. 1201-1204, May 1983.
4. T. Onomi, Y. Mizugaki, K. Nakajima, and T. Yamashita, "Design and fabrication of an adder circuit in the extended phase-mode logic," IEEE Trans. Appl. Superconduct., vol. 7, pp. 3172-3175, June 1997.
5. T. Onomi, Y. Mizugaki, H. Satoh, T. Yamashita, and K. Nakajima, "Phase-mode circuits for high-performance logic," IEICE Trans. Electron., vol. E81-C, pp. 1608-1617, Oct., 1998.
6. T. Onomi, K. Yanagisawa, and K. Nakajima, "New phase-mode logic gates with large operating regions of circuit parameters," IEEE Trans. Appl. Superconduct., vol. 11, pp. 974-977, March 2001.
7. T. Onomi, K. Yanagisawa, M. Seki, and K. Nakajima, "Phase-mode pipelined parallel multiplier," IEEE Trans. Appl. Superconduct., vol. 11, pp. 541-547, March 2001.
8. S. Nagasawa, Y. Hashimoto, H. Numata, and S. Tahara, "A 380ps, 9. 5mW Josephson 4-K bit RAM operated at a high bit yield," IEEE Trans. Appl. Superconduct., vol. 5, pp. 2447-2452, Jun. 1995.
9. Y. Horima, I. Shimizu, M. Kobori, T. Onomi, and K. Nakajima, "Comparison between an AND array and a Booth encoder for large-scale phase-mode multipliers," IEICE Trans. Electron., submitted for publication.