A 1.8 V monolithic CMOS nested-loop frequency synthesizer for GSM receivers at 1.8 GHz

IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers

Volumn , Issue , 2003, Pages 291-294

  Murji, Rizwan ^a   Deen, M Jamal ^a  

^a MCMASTER UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; GLOBAL SYSTEM FOR MOBILE COMMUNICATIONS; MIM DEVICES; SIGNAL RECEIVERS; SPURIOUS SIGNAL NOISE; VARIABLE FREQUENCY OSCILLATORS;

NESTED-LOOP FREQUENCY SYNTHESIZERS;

FREQUENCY SYNTHESIZERS;

EID: 0042023703     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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10. R. Murji, "A 1.8-V Monolithic CMOS Nested-Loop Frequency Synthesizer for GSM Receivers at 1.8-GHz," M.Sc. Thesis, McMaster University, December 2002.