Adding synchronous and LSSD modes to asynchronous circuits

Microprocessors and Microsystems

Volumn 27, Issue 9, 2003, Pages 461-471

  Van Berkel, Kees ^a,b   Peeters, Ad ^a   Te Beest, Frank ^c  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^c UNIVERSITY OF TWENTE   (Netherlands)

Author keywords

Asynchronous circuits; Level sensitive scan design; Shift register latches; Test pattern generation

Indexed keywords

COSTS; DELAY CIRCUITS; PRODUCT DESIGN; SHIFT REGISTERS;

ASYNCHRONOUS CIRCUITS;

DIGITAL CIRCUITS;

EID: 0041882135     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0141-9331(03)00095-4     Document Type: Conference Paper

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