Optimization of LDMOS array design for SOA and hot carrier lifetime

IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Volumn , Issue , 2003, Pages 84-87

  Strachan, Andy ^a   Brisbin, Doug ^a  

^a NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAYS; COMPUTER SIMULATION; ELECTRIC CURRENTS; GATES (TRANSISTOR); HOT CARRIERS; IMPACT IONIZATION;

DRIFT LENGTH;

MOSFET DEVICES;

EID: 0041438323     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Pendharkar et al. "Optimization of low voltage n-channel LDMOS devices to achieve required electrical and lifetime SOA". JSPSD 2002
2. Nehrer et al. "The Optimization of LBC6 Power/Mixed Signal IC BiCMOS Process", BCTM 2001
3. Strachan et al "A Trench-Isolated Power BiCMOS Process with Complementary High performance Bipolars", BCTM 2002
4. Nezar et al "Hot Electron Induced Snapback in 50V LDMOS Transistors Fabricated in a 0.8um CMOS Technology", BCTM 1996
5. Brisbin et al. "Hot Carrier Reliability of N-LDMOS Transistor Arrays for Power BiCMOS Applications ", Int'l Reliability Physics Symp. 2002.