Implementing a fully integrated IPA drying process in the fab environment

MICRO

Volumn 20, Issue 6, 2002, Pages 61-72

  Rosato, John J ^a   Yalamanchili, M Rao ^a   Baiya, Evanson G ^a   Hanson, Dwight J ^a   Eilmsteiner, Gerhard ^b   Petritsch, Andreas ^b  

^a Akrion   (United States)

^b SCP Global Technologies ^*  (India)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0041312116     PISSN: 10810595     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (12)

1. The International Technology Roadmap for Semiconductors (San Jose: Semiconductor Industry Association, 2001), 16.
2. L Peters, "Water Spots: The Scourge of Wafer Dryers, " Semiconductor International 21, no. 6 (1998): 83-90.
3. MR Yalamanchili, JJ Rosato, and J Prasad, "Drying Challenges for Sub-100-nm Device Processing: A Fundamental Look at the Inherent Disadvantages of Surface Tension Gradient Type IPA Dryers Vs. Vapor Condensation Type IPA Dryers" (paper presented at International Sematech's Wafer Cleaning and Surface Preparation Workshop, Austin, TX, May 21-22, 2002).
4. U.S. Patent 6, 328, 809 Bl.
5. MR Yalamanchili, JJ Rosato, and EG Baiya, "IPA Vapor Drying Technology to Meet Surface Preparation Challenges for Sub-0.18-μm Design Rules, " Future Fab International 9 (January 2000): 199-202.
6. SJ Buffat, MS Lucey, and MR Yalamanchili, "Advanced 300-mm Wafer Surface Preparation Methods for Sub-130-nm Device Processing, " Future Fab International 12 (February 2002): 221-227.
7. J McMurran and MR Yalamanchili, "Integration of SCI Process and Rinse Steps for Improved Surface Characteristics in Critical Cleans for Thin Gate Oxides, " in Proceedings of the Semicon Korea Technical Symposium (San Jose: SEMI, 2001), 73-81.
8. JJ Rosato et al., "Optimized Surface Preparation Technologies for Improved Gate Oxide Integrity in Thin Nitrided-Oxides, " Future Fab International 11 (June 2001): 219-225.
9. E Baiya et al., "Advanced Pre-Gate for High Quality Thin Oxides and Nitrided Oxides" (paper presented at the Electrochemical Society Joint International Meeting, San Francisco, September 2-7, 2001).
10. W Kern, Handbook of Semiconductor Wafer Cleaning Technology (Park Ridge, NJ: Noyes Publications, 1993), 182.
11. D Levy et al., "Dual Gate Oxide for 0.18 μm Technologies and Below: Optimization of the Wet Processing Sequence, " Solid State Phenomena 76 (2001): 27-30.
12. MR Yalamanchili et al., "Integration of Surface Passivation and Metals Cleaning Processes with Rinse/Dry Step" (paper presented at the 7th SCP International Symposium on Wafer Cleaning Technology, Boise, ID, May 2000).