Area-efficient memory-based architecture for FFT processing

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2003, Pages

  Moon, Sang Chul ^a   Park, In Cheol ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; COMMUNICATION SYSTEMS; FAST FOURIER TRANSFORMS; NETWORK PROTOCOLS;

PARALLEL ARCHITECTURE;

ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING;

EID: 0038758764     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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2. L. J. Cimini. Analysis and simulation of a digital mobile channel using orthogonal frequency division multiplexing. IEEE Trans. Commun., COM-33(7):665-675, Jul. 1985
3. M.Alard and R.Lasalle, Principles of modulation and channel coding for digital broadcasting for mobile receivers, ITU WARC-ORB Conference., Sep. 1988.
4. Shousheng He and Torkelson, M., Design and implementation of a 1024-point pipeline FFT processor.Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 131 -134, 1998
5. Bidet, E.; Castelain, D.; Joanblanq, C.; Senn, P. A fast single-chip implementation of 8192 complex point FFT,IEEE Journal of Solid-State Circuits, Vol. 30 Issue: 3, pp. 300-305, March 1995
6. Baas, B.M. A low-power, high-performance, 1024-point FFT processor. IEEE Journal of Solid-State Circuits, Vol. 34 Issue: 3 , pp/ 380-387 March 1999
7. J.W.Cooley and J.W.Tukey. An algorithm for machine computation of complex Fourier Series, Math. Comput., Vol. 19, 1965