An efficient reduced-order interconnect macromodel for time-domain simulation

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2003, Pages

  Palenius, Timo ^a   Roos, Janne ^a  

^a AALTO UNIVERSITY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; FREQUENCY DOMAIN ANALYSIS; MATRIX ALGEBRA; TRANSISTORS;

NONLINEAR CIRCUITS;

VLSI CIRCUITS;

EID: 0038757606     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. A. Odabasioglu, M. Celik, and L. T. Pileggi, "Prima: Passive reduced-order interconnect macromodeling algorithm," IEEE Trans. Computer-Aided Design, vol. 17, no. 8, pp. 645-654, Aug. 1998.
2. L. Chua and P. Lin, Computed-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques, Prentice-Hall, 1975.
3. Aplac Solutions Corporation, Finland, APLAC 7.80 Reference Manual and 7.80 User's Manual, 2002, http://www.aplac.com.
4. Y. Liu, L. T. Pileggi, and A. J. Strojwas, "ftd: Frequency to time domain conversion for reduced-order interconnect simulation," IEEE Trans. Circuits Syst. I, vol. 48, no. 4, pp. 500-506, Apr. 2001.
5. T. Palenius, J. Roos, and S. Aaltonen, "Development and comparison of reduced-order interconnect macromodels for time-domain simulation," in ICECS'02, Dubrovnik, 2002, vol. 2, pp. 757-760.
6. H. Shichman, "Integration system of a nonlinear network-analysis program," IEEE Trans. Circuit Theory, vol. 17, no. 3, pp. 378-386, Aug. 1970.
7. R. Achar, P. Gunupudi, M. Nakhla, and E. Chiprout, "Passive interconnect reduction algorithm for distributed/measured networks," IEEE Trans. Circuits Syst. II, vol. 47, no. 4, pp. 287-301, Apr. 2000.