Development and comparison of reduced-order interconnect macromodels for time-domain simulation

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 2002, Pages 757-760

  Palenius, Timo ^a   Roos, Janne ^a   Aaltonen, Sakari ^a  

^a AALTO UNIVERSITY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

FEATURE SIZES; FREQUENCY DOMAINS; INTERCONNECT NETWORKS; MACRO-MODELS; MEMORY CONSUMPTION; MODEL REDUCTION; NONLINEAR CIRCUIT; REDUCED ORDER; RLC NETWORKS; SIGNAL SPEED; SIMULATION TIME; TIME-DOMAIN SIMULATIONS;

COMPUTER SIMULATION; DIGITAL CIRCUITS; FREQUENCY DOMAIN ANALYSIS;

VLSI CIRCUITS;

EID: 0038329971     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2002.1046279     Document Type: Conference Paper

References (5)

1. A. Odabasioglu, M. Celik, and L. T. Pileggi, "PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm, " IEEE Trans. Computer-Aided Design, vol.17, no.8, pp. 645-654, Aug. 1998.
2. Aplac Solutions Corporation, Espoo, Finland, "APLAC - Circuit Simulation and Design Tool, " Espoo, Finland, 2001. Version 7.62 Manuals, http://www.aplac.com
3. Y. Liu, L. T. Pileggi, and A. J. Strojwas, "ftd: Frequency to Time Domain Conversion for Reduced-Order Interconnect Simulation, " IEEE Trans. Circuits Syst. I, vol.48, no.4, pp. 500-506, Apr. 2001.
4. P. Heikkilä, "Object-Oriented Approach to Numerical Circuit Analysis, " Doctoral Thesis, Helsinki University of Technology, 1992.
5. R. Achar, P. Gunupudi, M. Nakhla, and E. Chiprout, "Passive Interconnect Reduction Algorithm for Distributed/Measured Networks, " IEEE Trans, on Circuits Syst. II, vol.47, no.4, pp. 287-301, Apr. 2000.