A novel architecture for power maskable arithmetic units

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 2003, Pages 136-140

  Benini, L ^a   Macii, A ^b   Macii, E ^b   Omerbegovic, E ^c   Poncino, M ^d   Pro, F ^c  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b POLITECNICO DI TORINO   (Italy)

^c R and D Division   (Italy)

^d UNIVERSITY OF VERONA   (Italy)

Author keywords

Cryptography; Low Power Design; Security

Indexed keywords

CRYPTOGRAPHY; HARDWARE; LOGIC DESIGN; MASKS;

LOW-POWER DESIGN;

DIGITAL ARITHMETIC;

EID: 0038714059     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/764844.764845     Document Type: Conference Paper

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