Exact routing with search space reduction

IEEE Transactions on Computers

Volumn 52, Issue 6, 2003, Pages 815-825

  Schmiedle, Frank ^a   Drechsler, Rolf ^b   Becker, Bernd ^a  

^a UNIVERSITY OF FREIBURG   (Germany)

^b UNIVERSITY OF BREMEN   (Germany)

Author keywords

Detailed routing; Fixed point Iteration; Forced cells; MDDs

Indexed keywords

HEURISTIC METHODS; ROUTERS; SHORT CIRCUIT CURRENTS;

SEARCH SPACE;

VLSI CIRCUITS;

EID: 0038381549     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2003.1204836     Document Type: Article

References (22)

1. R.E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Trans. Computers, vol. 35, no. 8, pp. 677-691, Aug. 1986.
2. 20 States and Beyond," Information and Computation, vol. 98, no. 2, pp. 142-170, 1992.
3. S. Devadas, "Optimal Layout via Boolean Satisfiability," Proc. Int'l Conf. Computer Aided Design, pp. 294-297, 1989.
4. E.P. Huijbregts and J.A.G. Jess, "General Gate Array Routing Using a k-Terminal Net Routing Algorithm with Failure Prediction," IEEE Trans. VLSI Systems, vol. 1, no. 4, pp. 473-481, 1993.
5. R. Joobbani, An Artificial Intelligence Approach to VLSI Routing. Kluwer Academic, 1986.
6. A.B. Kahng and G. Robins, On Optimal Interconnections for VLSI. first ed. Kluwer Academic, 1995.
7. T. Kam, T. Villa, R. Brayton, and A. Sangiovanni-Vincentelli, "Multi-Valued Decision Diagrams: Theory and Applications," Multiple Valued Logic - An Int'l J., pp. 9-62, 1998.
8. R.K. Korn, "An Efficient Variable-Cost Maze Router," Proc. 19th Design Automation Conf., pp. 425-431, 1982.
9. C.Y. Lee, "An Algorithm for Path Connections and Its Applications," IRE Trans. Electronic Computers, vol. 10, no. 3, pp. 346-365, 1961.
10. T. Lengauer, Combinatorial Algorithms for Integrated Circuit Layout. Teubner, Wiley, 1990.
11. P. Mazumder and E. Rudnick, Genetic Algorithms for VLSI Design, Layout and Test Automation. Prentice Hall, 1999.
12. K.L. MCMillan, Symbolic Model Checking. Kluwer Academic, 1993.
13. G.-J. Nam, K.A. Sakallah, and R.A. Rutenbar, "Satisfiability-Based Layout Revisted: Detailed Routing of Complex FPGAs via Search-Based Boolean Sat," Proc. Int'l Symp. FPGAs for Custom Computing Machines, pp. 167-175, 1999.
14. S.M. Sait and H. Youssef, VLSI Physical Design Automation, Springer Verlag, 1999.
15. M. Sarrafzadeh and D.T. Lee, Algorithmic Aspects of VLSI Layout, Springer Verlag, 1993.
16. F. Schmiedle, R. Drechsler, and B. Becker, "Exact Routing Using Symbolic Representation," Proc. Int'l Symp. Circuits and Systems, pp. 394-397, 1999.
17. F. Schmiedle, D. Unruh, and B. Becker, "Exact Switchbox Routing with Search Space Reduction," Proc. Int'l Symp. Physical Design, pp. 26-32, 2000.
18. N. Sherwani, Algorithms for VLSI Physical Design Automation, second ed. Norwell, Mass.: Kluwer Academic, 1995.
19. F. Somenzi, CUDD: CU Decision Diagram Package Release 2.3.0. Univ. of Colorado at Boulder, 1998.
20. A. Srinivasan, T. Kam, S. Malik, and R.E. Brayton, "Algorithms for Discrete Function Manipulation," Proc. Int'l Conf. Computer Aided Design, pp. 92-95, 1990.
21. T.G. Szymanski, "Dogleg Channel Routing is NP-Complete," IEEE Trans. Computer Aided Design, vol. 4, no. 1, pp. 31-41, 1985.
22. R.G. Wood and R.A. Rutenbar, "FPGA Routing and Routability Estimation via Boolean Satisfiability," IEEE Trans. VLSI Systems, vol. 6, no. 2, pp, 222-231, 1998.