PartGen: a generator of very large circuits to benchmark the partitioning of FPGAs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 11, 2000, Pages 1314-1321

  Pistorius, Joachim ^a   Legai, Edmée ^b   Minoux, Michel ^c  

^a Lattice Semiconductor Corporation   (United States)

^b MENTOR GRAPHICS CORPORATION   (United States)

^c SORBONNE UNIVERSITÉ   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BENCHMARKING; COMBINATORIAL CIRCUITS; COMPUTER WORKSTATIONS; FIELD PROGRAMMABLE GATE ARRAYS; UNIX;

PARTITIONING; RANDOM CIRCUIT GENERATION;

VLSI CIRCUITS;

EID: 0034313532     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.892855     Document Type: Article

References (16)