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Volumn 150, Issue 3, 2003, Pages 161-166

Designing robust asynchronous circuit components

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC DESIGN; LOGIC GATES; MATHEMATICAL MODELS; PROBLEM SOLVING; SYNCHRONIZATION;

EID: 0038148544     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:20030349     Document Type: Article
Times cited : (8)

References (8)
  • 3
    • 0026882866 scopus 로고
    • Beware the isochronic fork
    • van Berkel, C.H.: 'Beware the isochronic fork'. Integr. VLSI J., 1992, 13, (3), pp. 103-129
    • (1992) Integr. VLSI J. , vol.13 , Issue.3 , pp. 103-129
    • Van Berkel, C.H.1
  • 6
    • 0022700785 scopus 로고
    • Design-performance trade-offs in CMOS-domino logic
    • Oklobdzija, V.G., and Montoye, R.K.: 'Design-performance trade-offs in CMOS-domino logic', IEEE J. Solid-State Circuits, 1986, 21, (2), pp. 304-306
    • (1986) IEEE J. Solid-State Circuits , vol.21 , Issue.2 , pp. 304-306
    • Oklobdzija, V.G.1    Montoye, R.K.2
  • 7
    • 0004001955 scopus 로고
    • Simulation program with integrated circuit emphasis (SPICE)
    • Report ERLM383, Electronics Research Laboratory, University of California, Berkeley
    • Nagel, L.W., and Pederson, D.O.: 'Simulation program with integrated circuit emphasis (SPICE)'. Report ERLM383, Electronics Research Laboratory, University of California, Berkeley, 1983
    • (1983)
    • Nagel, L.W.1    Pederson, D.O.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.