Design of ultra high-speed CMOS CML buffers and latches

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2003, Pages

  Heydari, Payam ^a   Mohavavelu, Ravi ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC INVERTERS; ELECTRIC POTENTIAL; FLIP FLOP CIRCUITS; MATHEMATICAL MODELS; RESISTORS; SWITCHING; TRANSCEIVERS;

CURRENT-MODE LOGIC (CML);

BUFFER CIRCUITS;

EID: 0038084264     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. J. Rabaey, Digital Integrated Circuits: A Design Perspective, Prentice-Hall, 1996.
2. B. Razavi, "Prospects of CMOS Technology for High-Speed Optical Communication Circuits," IEEE J. Solid-State Circuits, vol. 37, No. 9, pp. 1135-1145, Sept. 2002.
3. M. Mizuno, M. Yamashina, K. Furuta, H. Igura, H. Abiko, K. Okabe, A. Ono, H. Yamada, "A GHz MOS adaptive pipeline technique using MOS current-mode logic," IEEE J. Solid-State Circuits, vol. 31, No. 6, pp. 784-791, June 1996.
4. M. H. Anis, M. I. Elmasry, "Self-timed MOS current mode logic for digital applications," IEEE Int'l Symp. on Circuits and Systems, vol. 5, pp. 113-116, May 2002.
5. B. Razavi, Design of Analog CMOS Integrated Circuits, pp. 101-134, McGraw-Hill, 2001.
6. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, 1998.
7. N. Hedenstierna, K. O. Jeppson, "CMOS Circuit Speed and Buffer Optimization," IEEE Trans. Computer-Aided Design, vol. CAD-6, No. 2, pp. 270-281, March 1987.