Application of Cr-less mask technology for sub-100 nm gate with single exposure

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 4889, Issue 1, 2002, Pages 568-578

  Kim, Sung Hyuck ^a   Chung, Dong Hoon ^a   Park, Ji Soong ^a   Shin, In Kyun ^a   Choi, Seong Woon ^a   Sohn, Jung Min ^a   Lee, Jae Han ^a   Shin, Hye Soo ^a   Chen, Fung ^b   Van Den Broeke, Douglas ^b  

^a SAMSUNG Electronics   (South Korea)

^b Masktools   (United States)

Author keywords

CPL; KrF; OAI; OPC; PEPSM; RET

Indexed keywords

COMPUTER SIMULATION; IMAGE ANALYSIS; PHASE SHIFT; PHOTOLITHOGRAPHY; SEMICONDUCTOR DEVICE MANUFACTURE;

PHASE CONFLICTS;

MASKS;

EID: 0037965971     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.468097     Document Type: Conference Paper

References (7)

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4. K. Watanabe et al., "Sub-quarter-micron gate pattern fabrication using a transparent phase shifting mask", J. Vac.Sci. Technology, B9 (6), Nov./Dec. (1991)
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6. J. Fung Chen et. al., "Binary halftone chromeless PSM technology for λ/4 optical lithography", Proc.SPIE, Vol. 4346, pp515-533 (2001)
7. J. H. Park et. al., "The development of mask-making process for CPL manufacturing technology", Proc.SPIE, Vol. 4754, pp727-736 (2002)