Prizma switch technology

IBM Journal of Research and Development

Volumn 47, Issue 2-3, 2003, Pages 195-209

  Engbersen, Antonius P J ^a  

^a IBM RESEARCH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

INTERFACES (COMPUTER); INTERNET; LIGHT TRANSMISSION; WAVELENGTH DIVISION MULTIPLEXING;

SWITCH-CHIP PRODUCTS;

PACKET SWITCHING;

EID: 0037809811     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.472.0195     Document Type: Review

References (36)

1. "The Network Letter: IP Traffic Growth - Revisited," The ATM & IP Report, July/August 2001, Broadband Publishing; see http://www.broadbandpub.com/atmreport/.
2. W. Bux, W. E. Denzel, T. Engbersen, A. Herkersdorf, and R. Luijten, "Technologies and Building Blocks for Fast Packet Forwarding," IEEE Commun. Mag. 39, 2-9 (January 2001).
3. J. K. Patel, "Performance of Processor-Memory Interconnections for Multiprocessors," IEEE Trans. Computing 30, No. 10, 771-780 (October 1981).
4. M. J. Karol, M. G. Hluchyj, and S. P. Morgan, "Input vs. Output Queuing on a Space-Division Packet Switch," IEEE Trans. Commun. 35, No. 12, 1347-1356 (1987).
5. Y. Yen, M. G. Hluchyj, and A. S. Acampora, "The Knockout Switch: A Simple, Modular Architecture for High-Performance Packet Switching," IEEE J. Sel. Areas Commun. 5, No. 8, 1274-1283 (October 1987).
6. H. Suzuki, H. Nagano, and T. Suzuki, "Output Buffered Switch Architecture for Asynchronous Transfer Mode," Proceedings of the International Communications Conference (ICC'89), Boston, June 1989, pp. 99-103.
7. H. Ahmadi, W. E. Denzel, C. A. Murphy, and E. Port, "A High-Performance Switch Fabric for Integrated Circuit andPacket Switching," Proceedings of the IEEE Conference on Computer Communications (INFOCOM'88), New Orleans, March 1988, pp. 9-18.
8. W. E. Denzel, A. P. J. Engbersen, I. Iliadis, and G. Karlsson, "Highly Modular Packet Switch for Gb/s Rates," Proceedings of the International Communications Conference (ICC'92), Yokohama, Japan, October 25-30, 1992, pp. 237-240.
9. R. J. McMillen, "Packet Switched Multiple Queue N × M Switch Node and Processing Method," U.S. Patent 4,623,996, filed October 18, 1984; published November 18, 1986.
10. Y. Tamir and G. Frazier, "High-Performance Multi-Queue Buffers for VLSI Communication Switches," Proceedings of the 15th International Symposium on Computer Architecture (ACM SIGARCH), Vol. 16, No. 2, May 1988, pp. 343-354.
11. R. O. LaMaire and D. N. Serpanos, "Two-Dimensional Round-Robin Schedulers for Packet Switches with Multiple Input Queues," IEEE/ACM Trans. Networking 2, No. 5, 471-482 (October 1994).
12. C. Lund, S. Phillips, and N. Reingold, "Fair Prioritized Scheduling in an Input-Buffered Switch," Proceedings of the Conference on Broadband Communications, Montreal, Canada, 1996, pp. 358-369.
13. N. W. McKeown, "Scheduling Algorithms for Input-Queued Switches," Ph.D. thesis, University of California, Berkeley, 1995.
14. N. W. McKeown, "The iSLIP Scheduling Algorithm for Input-Queued Switches," IEEE/ACM Trans. Networking 7, No. 2, 188-201 (April 1999).
15. N. W. McKeown, "Fast Switched Backplane for a Gigabit Switched Router," Cisco Systems white paper; see http:// www.cisco.com/warp/public/cc/cisco/mkt/core/12000/tech/fasts_wp.pdf.
16. D. N. Serpanos and P. I. Antoniadis, "Firm: A Class of Distributed Scheduling Algorithms for High-Speed ATM Switches with Multiple Input Queues," Proceedings of the IEEE Conference on Computer Communications (INFOCOM 2000), Tel Aviv, Israel, March 2000, Vol. 2, pp. 548-555.
17. I. Stoica and H. Zhang, "Exact Emulation of an Output Queuing Switch by a Combined Input Output Queuing Switch," Proceedings of the Sixth IEEE/IFIP Workshop on Quality of Service (IWQoS'98), Napa Valley, CA, May 1998, pp. 218-224.
18. H. Kuwahara, N. Endo, M. Ogino, and T. Kozaki, "A Shared Buffer Memory Switch for an ATM Exchange," Proceedings of the International Communications Conference (ICC'89), Boston, June 1989, pp. 118-122.
19. T. Kozaki, N. Endo, Y. Sakurai, O. Matsubara, M. Mizukami, and K. Asano, "32 × 32 Shared Buffer Type ATM Switch VLSI's for B-ISDN's," IEEE J. Sel. Areas Commun. 9, No. 8, 1239-1247 (October 1991).
20. C. B. Stunkel, D. G. Shea, B. Abali, M. G. Atkins, C. A. Bender, D. G. Grice, P. Hochschild, D. J. Joseph, B. J. Nathanson, R. A. Swetz, R. F. Stucke, M. Tsao, and P. R. Varker, "The SP2 High-Performance Switch," IBM Syst. J. 34, No. 2, 185-204 (1995).
21. M. Katevenis, D. Serpanos, and P. Vatsolaki, "ATLAS I: A General-Purpose, Single-Chip ATM Switch with Credit-Based Flow Control," presented at the IEEE Hot Interconnects IV Symposium, Stanford, CA, August 15-17, 1996.
22. G. Kornaros, D. Pnevmatikatos, P. Vatsolaki, G. Kalokerinos, C. Xanthaki, D. Mavroidis, D. Serpanos, and M. Katevenis, "ATLAS I: Implementing a Single-Chip ATM Switch with Backpressure," IEEE Micro Mag., pp. 30-41 (January-February 1999).
23. W. E. Denzel, A. P. J. Engbersen, and I. Iliadis, "A Flexible Shared-Buffer Switch for ATM at Gb/s Rates," Computer Networks & ISDN Syst. 27, No. 4, 611-624 (January 1995).
24. A. P. J. Engbersen, "Multicast/Broadcast Mechanism for a Shared Buffer Packet Switch," IBM Tech. Disclosure Bull. 34, No. 10a, 464-465 (March 1992).
25. H. Ahmadi, W. E. Denzel, C. A. Murphy, and E. Port, "A High-Performance Switch Fabric for Integrated Circuit and Packet Switching," Int. J. Digital & Analog Cabled Syst. 2, No. 4, 277-287 (1989).
26. H. Ahmadi, J. G. Beha, W. E. Denzel, A. P. Engbersen, R. P. Luijten, C. A. Murphy, and E. Port, "High-Speed Modular Switching Apparatus for Circuit and Packet Switched Traffic," U.S. Patent 5,008,878, April 16, 1991.
27. P. Austruy, A. Fichou, C. Galand, and I. Iliadis, "Back Pressure Access Control System for a Shared Buffer with Allocation Threshold for each Traffic Class," U.S. Patent 5,838,922, 1999.
28. M. Colmant and R. P. Luijten, "A Single-Chip Lossless 16 × 16 Switch Fabric with 28 Gb/s Throughput," Research Report RZ-3087, IBM Zurich Research Laboratory, Rüschlikon, Switzerland, December 1998.
29. C. Minkenberg and T. Engbersen, "A Combined Input-and Output-Queued Packet-Switch System Based on PRIZMA Switch-on-a-Chip Technology," IEEE Commun. Mag. 38, No. 12, 70-77 (December 2000).
30. C. Minkenberg, "On Packet Switch Design," Ph.D. thesis, Technical University Eindhoven, The Netherlands, September 2001; also available as IBM Research Report RZ-3387, 2001.
31. C. Minkenberg, "On Packet Switch Design," Ph.D. thesis, Technical University Eindhoven, The Netherlands, September 2001; also available as IBM Research Report RZ-3387, 2001.
32. I. Iliadis, "Performance of a Packet Switch with Shared Buffer and Input Queueing," Teletraffic and Datatraffic in a Period of Change (ITC-13), Copenhagen, Denmark, June 1991, A. Jensen and V. B. Iversen, Eds., Elsevier, Amsterdam, 1991, pp. 911-916.
33. R. P. Luijten, T. Engbersen, and C. Minkenberg, "Shared Memory Switching + Virtual Output Queuing: a Robust and Scalable Switch," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Sydney, Australia, May 2001 (IEEE, Piscataway, NJ, 2001), pp. IV-274-IV-277.
34. R. Bakka and M. Dieudonne, "Switching Circuit for Digital Packet Switching Network," U.S. Patent 4,314,367, February 2, 1982.
35. S. Nojima, Y. Kato, T. Shimoe, K. Hajikano, and K. Murakami, "Experimental Broadband ATM Switching System," Proceedings of the IEEE Global Telecommunications Conference (GLOBECOM'88), Hollywood, FL, November 1988, pp. 1288-1292.
36. K. Yoshigoe and K. J. Christensen, "A Parallel-Polled Virtual Output Queued Switch with a Buffered Crossbar," Proceedings of the Workshop on High Performance Switching and Routing, Dallas, TX, May 2001, pp. 271-275.