A highly scalable 3D chip for binary neural network classification applications

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2003, Pages

  Bermak, Amine ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

MULTICARRIER MODULATION; TOPOLOGY; VLSI CIRCUITS;

MULTIPRECISION NEURAL CHIPS;

NEURAL NETWORKS;

EID: 0037743771     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. P. D. Franzon, MultiChip Module Technologies and Alternatives, New York: Van Nostrand Reinhold, 1993, ch. 3, pp. 102-106.
2. C. Campbell, Constructive Learning Techniques for Designing Neural Network Systems: A review of constructive learning techniques, Neural Network Systems, Techniques and Applications, ed. C.T. Leondes, Academic Press, San Diego, 1996.
3. M. Muselli, On sequential construction of binary neural networks, IEEE Trans. Neural Networks, vol. 6, no. 3, May 1995.
4. J. M. T. Moreno und M. B. Gordon, Efficient adaptive learning for classification tasks with binary units, Neural Computation, 10(4), pp.1007-1030, 1998.
5. L. Breiman, J. H. Friedman, R. A. Olshen and C. J. Stone, Classification and regression trees, Wadsworth Int. Group, Bolmont CA, 1984.
6. S.P. Larcombe, P.A. Ivey, N.L. Seed, J.M. Stern and C.M. Val, Electronic systems in dense three-dimensional packages, Electronics Letters, Vol.31, N.10, pp.786-788, June 1995.