A mixed-mode ESD protection circuit simulation-design methodology

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 6, 2003, Pages 995-1006

  Feng, Haigang ^a   Chen, Guang ^a   Zhan, Rouying ^a   Wu, Qiong ^a   Guan, Xiaokang ^a   Xie, Haolu ^a   Wang, Albert Z H ^a   Gafiteanu, Roman ^b  

^a Illinois Institute of Technology   (United States)

^b SYNOPSYS INC   (United States)

Author keywords

BiCMOS; CMOS; Electrostatic discharge (ESD) protection; Mixed mode; Mixed signal; NMOS

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC EQUIPMENT PROTECTION; ELECTRIC LOSSES; ELECTROSTATICS;

ELECTROSTATIC DISCHARGE (ESD) PROTECTION;

ELECTRIC DISCHARGES;

EID: 0037704357     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.811978     Document Type: Article

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