A 13.3Mb/s 0.35μm CMOS analog turbo decoder IC with a configurable interleaver

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Gaudet, Vincent C ^a   Gulak, P Glenn ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; COMPUTER PROGRAMMING LANGUAGES; DECODING; DEMULTIPLEXING; FEEDBACK; SIGNAL TO NOISE RATIO;

ANALOG TURBO DECODERS; DIGITAL TURBO DECODERS; ITERATIVE DECODING; MAXIMUM A POSTERIORI; RECURSIVE SYSTEM CONVOLUTIONAL;

TURBO CODES;

EID: 0037630981     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. C. Berrou et al., "An IC for Turbo-Codes Encoding and Decoding," ISSCC Digest of Technical Papers, pp. 90-91, Feb. 1995.
2. M. Bekooij et al., "Power-Efficient Application-Specific VLIW Processor for Turbo Decoding," ISSCC Digest of Technical Papers, pp. 180-181, Feb. 2001.
3. M. Bickerstaff et al., "A Unified Turbo / Viterbi Channel Decoder for 3GPP Mobile Wireless in 0.18μm CMOS," ISSCC Digest of Technical Papers, pp. 90-91, Feb. 2002.
4. M. Moerz et al., "An Analog 0.25μm BiCMOS Tailbiting MAP Decoder," ISSCC Digest of Technical Papers, pp. 356-357, Feb. 2000.