Novel low capacitance sidewall elevated drain dynamic threshold voltage MOSFET (LCSED) for ultra low power dual gate CMOS technology

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1998, Pages 415-418

  Kotaki, H ^a   Kakimoto, S ^a   Nakano, M ^a   Adachi, K ^a   Shibata, A ^a   Sugimoto, K ^a   Ohta, K ^a   Hashizume, N ^a  

^a SHARP CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; THRESHOLD VOLTAGE;

LOW CAPACITANCE SIDEWALL ELEVATED DRAIN (LCSED);

MOSFET DEVICES;

EID: 0032255093     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)