A low-power low-jitter adaptive-bandwidth PLL and clock buffer

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Mansuri, Mozhgan ^a   Yang, Chih Kong Ken ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); BUFFER CIRCUITS; COMPUTER SIMULATION; ELECTRIC CONDUCTIVITY; ELECTRIC IMPEDANCE; FREQUENCY DIVIDING CIRCUITS; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE; TIMING CIRCUITS; VARIABLE FREQUENCY OSCILLATORS;

CLOCK BUFFER; CURRENT CONTROLLED OSCILLATOR; LOW-POWER DIGITAL SYSTEM; PHASE FREQUENCY DETECTOR; PROGRAMMABLE PASSIVE CIRCUIT; PSEUDO-DIFFERENTIAL INVERTER;

ELECTRIC NETWORK SYNTHESIS;

EID: 0037630667     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. V. Gutnik, et al., "Embedded Power Supply for Low-Power DSP," IEEE Trans-VLSI, pp. 425-435, Dec. 1997.
2. K.Y.K. Chang, et al., "A 0.4-Gb/s CMOS Quad Transceiver Cell using On-chip Regulated Dual-Loop PLLs," 2002 VLSI Symposium, pp. 88-91.
3. K. Minami, et al., "A 0.10μm CMOS 1.2V, 2GHz Phase-Locked Loop with Gain Compensation VCO," 2001 CICC, pp. 213-216.
4. H. Ahn, et al., "A Low-Jitter 1.9-V CMOS PLL for UltraSPARC Microprocessor Applications," J. Solid State Circuits, vol. 35, pp. 450-454, March 2000.
5. S. Sidiropoulos, et al., "Adaptive Bandwidth DLL's and PLL's using Regulated Supply CMOS Buffers," 2000 VLSI Symposium, pp. 124-127.
6. P. Larsson, "A 2-1600-MHz CMOS Clock Recovery PLL with Low-Vdd Capability," J. Solid State Circuits, vol. 34, pp. 1951-1960, Dec. 1999.