Optimal circuit clustering for delay minimization under a more general delay model

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 5, 2003, Pages 646-652

  Sze, C N ^a   Wang, Ting Chi ^b  

^a TEXAS A AND M UNIVERSITY   (United States)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Partitioning; Performance optimization; Physical design; Timing optimization; Very large scale integration (VLSI)

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; COMPUTER AIDED DESIGN; CONSTRAINT THEORY; DELAY CIRCUITS; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; OPTIMIZATION; POLYNOMIALS; PROBLEM SOLVING; THEOREM PROVING; VLSI CIRCUITS;

INTERCONNECT DELAY; PHYSICAL DESIGN; VERTEX GROUPING TECHNIQUE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0037515471     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.810746     Document Type: Article

References (4)

1. R. Rajaraman and D. F. Wong, "Optimum clustering for delay minimization," IEEE Trans. Computer-Aided Design, vol. 14, pp. 1490-1495, Dec. 1995.
2. H. Yang and D. F. Wong, "Circuit clustering for delay minimization under area and pin constraints," IEEE Trans. Computer-Aided Design, vol. 16, pp. 976-986, Sept. 1997.
3. R. Murgai, R. K. Brayton, and A. Sangiovanni-Vincentelli, "On clustering for minimum delay/area," in Proc. IEEE Int. Conf. Computer-Aided Design, 1991, pp. 6-9.
4. E. Lawler, K. Levitt, and J. Turner, "Module clustering to minimize delay in digital networks," IEEE Trans. Comput., vol. C-18, pp. 47-57, Jan. 1966.