Circuit clustering for delay minimization under area and pin constraints

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 9, 1997, Pages 976-986

  Yang, Hannah Honghua ^a   Wong, D F ^a  

^a University of Texas at Austin   (United States)

Author keywords

Circuit netlist; Clustering; Delay minimization; Network flow; Partitioning

Indexed keywords

ALGORITHMS; COMPUTER AIDED LOGIC DESIGN; DELAY CIRCUITS; INTEGRATED CIRCUIT LAYOUT; MULTICHIP MODULES;

CIRCUIT CLUSTERING; CIRCUIT PARTITIONING; DELAY MINIMIZATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

LOGIC GATES;

EID: 0031220656     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.658566     Document Type: Article

References (9)

1. R. K. Brayton. Rudell, and A. L. Sangiovanni-Vincentelli, "MIS: A multiple-level logic optimization," IEEE Trans. Computer-Aided Design, pp. 1061-1081, Nov. 1987.
2. J. Cong and Y. DingAn optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs," in Proc. IEEE Int. Conf. Computer-Aided Design, Nov. 1992, pp. 48-53.
3. S. Evenraph Algorithms. Rockville, MD: Computer Science, 1979.
4. J. R. Ford and D. R. Fulkersonlows in Networks. Princeton, NJ: Princeton University Press, 1962.
5. C. M. Fiduccia and R. M. MattheysesA linear time heuristic for improving network partitions," in Proc. ACM/IEEE Design Automation Conf., 1982, pp. 175-181.
6. E. L. Lawler. N. Levitt, and J. Turner, "Module clustering to minimize delay in digital networks," IEEE Trans. Comput., vol. C-18, 1966.
7. R. Murgai. K. Brayton, and A. Sangiovanni-Vincentelli, "On clustering for minimum delay/area," in Proc. IEEE Int. Conf. Computer-Aided Design, 1991, pp. 6-9.
8. B. Preas and M. Lorenzettihysical Design Automation of VLSI Systems. New York: Benjamin/Cummings, 1988.
9. R. Rajaraman and D. F. WongOptimal clustering for delay minimization," in Proc. 30th ACM/IEEE Design Automation Conf., 1993, pp. 309-314.