A branch and bound algorithm to minimize completion time variance on a single processor

Computers and Operations Research

Volumn 30, Issue 8, 2003, Pages 1135-1150

  Viswanathkumar, G ^a   Srinivasan, G ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY MADRAS   (India)

Author keywords

Branch and bound; Completion time variance; Lower bound; Single machine scheduling

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTATIONAL METHODS; COMPUTER SIMULATION; OPTIMIZATION; POLYNOMIALS; RANDOM ACCESS STORAGE; SCHEDULING; SIMULATED ANNEALING;

MACHINE SCHEDULING;

ALGORITHMS;

ALGORITHM;

EID: 0037410975     PISSN: 03050548     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0305-0548(02)00062-X     Document Type: Article

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