TEG: A new post-layout optimization method

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 4, 2003, Pages 446-456

  Zhang, Shuo ^a   Dai, Wayne ^a  

^a University of California Santa Cruz   (United States)

Author keywords

Optimization; Post layout; Topological layout

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK TOPOLOGY; ELECTRONICS INDUSTRY; GRAPH THEORY; NUMERICAL METHODS; OPTIMIZATION; VLSI CIRCUITS;

POST LAYOUT OPTIMIZATION; TOPOLOGICAL LAYOUT; TRIANGULATION ENCODING GRAPH;

INTEGRATED CIRCUIT LAYOUT;

EID: 0037390344     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.809652     Document Type: Article

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