TEG: A new post-layout optimization method

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2002, Pages 62-67

  Zhang, Shuo ^a   Dai, Wayne W M ^a  

^a University of California   (United States)

Author keywords

Algorithms

Indexed keywords

ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; ROUTERS; TOPOLOGY;

DESIGN OPTIMIZATION;

VLSI CIRCUITS;

EID: 0036375782     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. On crossing minimization problem
2. A faster one-demensional topological compaction algorithm withjog insertion
3. A provably good multilayer topological planar routing algorithm in IC layout design
4. On the k-layer subset and topological via minimization problems
5. Rubber band routing and dynamic data representation
6. Topological channel routing
7. Algorithms for routing and testing routability of planar VLSI layouts
8. Planar topological routing
9. Surf: A rubber-band routing system for multichip modules
10. Two-dimensional IC layout compaction based on topological design rule checking