A nonlinear capacitance cancellation technique and its application to a CMOS class AB power amplifier

IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers

Volumn , Issue , 2001, Pages 39-42

  Wang, C ^a   Larson, L E ^a   Asbeck, P M ^a  

^a University of California at San Diego   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC IMPEDANCE; ELECTRIC POTENTIAL; EQUIVALENT CIRCUITS; INTEGRATED CIRCUIT LAYOUT; MOSFET DEVICES;

CMOS CLASS AB POWER AMPLIFIER; NONLINEAR CAPACITANCE CANCELLATION TECHNIQUE; NONLINEAR INPUT CAPACITANCE; NONLINEAR INPUT IMPEDANCE;

POWER AMPLIFIERS;

EID: 0034869908     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. A 2.5-V, 1-W monolithic CMOS RF power amplifier
2. A 1 W 830 MHz monolithic BiCMOS power amplifier
3. Low voltage, high efficiency GaAs class E power amplifiers for wireless transmitters
4. Transmitter linearization using Cartesian feedback for linear TDMA modulation
5. A LINC transmitter
6. Amplifier linearization using a digital predistorter with fast adaption and low memory requirements