Methodical low-power ASIP design space exploration

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 33, Issue 3, 2003, Pages 229-246

  Glökler, Tilman ^a   Hoffmann, Andreas ^a   Meyr, Heinrich ^a  

^a RWTH AACHEN UNIVERSITY   (Germany)

Author keywords

Application specific instruction set processor; ASIP; ICORE; LISA; Low energy; Low power

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY CONSERVATION; LOGIC DESIGN; LUNAR MISSIONS; OPTIMIZATION; SEMICONDUCTING SILICON; SPACE APPLICATIONS;

APPLICATION-SPECIFIC INSTRUCTION SET PROCESSORS; CLOCK-GATING; INSTRUCTION SET ARCHITECTURE DESCRIPTION LANGUAGE; LOW ENERGY; LOW POWER;

INTEGRATED CIRCUIT LAYOUT;

EID: 0037335358     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1022167611720     Document Type: Article

References (28)

1. A. Abnous and J. Rabaey, "Ultra-Low-Power Domain-Specific Multimedia Processors," in Proc. IEEE VLSI Sig. Proc. Workshop, San Francisco, California, USA, Oct. 1996.
2. A. Hoffmann, O. Schliebusch, A. Nohl, G. Braun, O. Wahlen, and H. Meyr, "A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) Using the Machine Description Language LISA," IEEE Transactions On Computer Aided Design, forthcoming.
3. A. Hoffmann, A. Nohl, and H. Meyr, "A Survey on Modeling Issues Using the Machine Description Language LISA," in Proceedings of the International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Salt Lake City, May 2001.
4. T. Glökler, S. Bitterlich, and H. Meyr, "DSP Core Verification Using Automatic Test Case Generation," in Int. Conf. on Acoustics, Speech, and Signal Processing 2000, Istanbul, Turkey, June 2000.
5. M.K. Jain, M. Balakrishnan, and A. Kumar, "ASIP Design Methodologies : Survey and Issues," in Proc. of 14th CSI/IEEE Intl. Conf. on VLSI Design, Bangalore, India, Jan. 2001.
6. M. Itoh, et al., "PEAS-III: An ASIP Design Environment," in 2000 IEEE Int. Conf. on Computer Design: VLSI in Computers & Processors, Sep. 2000, pp. 430-436.
7. J.-H. Yang et al., "MetaCore: An Application-Specific Programmable DSP Development System," in IEEE Transactions on Very Large Scale Integration Systems, vol. 8, no. 2, April 2000, pp. 173-183.
8. G. Hadjiyiannis, P. Russo, and S. Devadas, "A Methodology for Accurate Performance Evaluation in Architecture Exploration," in 36th Design Automation Conference, New Orleans, June 1999.
9. F. Onion, A. Nicolau, and N. Dutt, "Incorporating Compiler Feedback Into the Design of ASIPs," in Proc. of European Design and Test Conference, 1995, pp. 508-513.
10. R. Leupers, Retargetable Code Generation for Digital Signal Processors, Kluwer Academic Publishers, 1997.
11. M. Santarini, http://www.eetimes.com/story/OEG20001120S-0028, 2000.
12. J. Scott, L.H. Lee, J. Arends, and Bill Moyer, "Designing the Low-Power M•Core Architecture," M•Core Technology Center; Motorola Inc., www.not.com/SPS/MCORE/pdf_container/lowpower.pdf, 04.04.2001.
13. S. Pees, A. Hoffmann, V. Zivojnovic, and H. Meyr, "LISA-Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures," in 36th Design Automation Conference, New Orleans, June 1999.
14. T. Glökler and S. Bitterlich, "Power Efficient Semi-Automatic Instruction Encoding for Application-Specific Instruction Set Processors," in Int. Conf. on Acoustics, Speech, and Signal Processing 2001, Salt Lake City, Utah, USA, May 2001.
15. http://www.synopsys.com, Synopsys Inc., Mountain View, CA, USA, 2001.
16. V. Tiwari, D. Singh, S. Rajgopal, G. Mehta, R. Patel, and F. Baez, "Reducing Power in High-Performance Microprocessors," in 35th Design Automation Conference, CA, USA, June 1998.
17. V. Tiwari, S. Malik, A. Wolfe, and T.C. Lee, "Instruction Level Power Analysis and Optimization of Software," Journal of VLSI Signal Processing Systems, vol. 13, no. 2, Aug. 1996.
18. http://www.sequencedesign.com, Sequence Design Inc., Santa Clara, CA, USA, 2001.
19. T. Glökler, S. Bitterlich, and H. Meyr, "Increasing the Power Efficiency of Application-Specific Instruction Set Processors Using Data-Path Optimization," in 2000 IEEE Workshop on Signal Processing, Lafayette, Louisiana, USA, Oct. 2000.
20. "Product Brief SQC 6100-Terrestrial Receiver for DVB-T," Infineon AG, Germany, www.infineon.com/products/ics/pdf/sqc_10b.pdf, 2000.
21. J.E. Volder, "The CORDIC Trigonometric Computing Technique," IRE Trans. on Electron. Computers, vol. EC-8, no. 3, 1959, pp. 330-334.
22. O. Wahlen, T. Glökler, A. Nohl, A. Hoffmann, R. Leupers, and H. Meyr, "Application Specific Architecture/Compiler Code-sign: A Case Study," Scopes Workshop 2002, Berlin, Germany, June 2002.
23. T. Claasen, "High Speed: Not the Only Way to Exploit the Intrinsic Computational Power of Silicon," in Int. Solid State Circ. Conf. 97, Digest of Tech. Papers, 1997.
24. G.K. Yeap, Practical Low Power Digital Design, Kluwer Academic Publishers, 1998.
25. W.E. Dougherty and D.E. Thomas, "Modeling and Automating Selection of Guarding Techniques for Datapath Elements," in Int. Symposium on Low Power Electronics and Design, ISLPED99, San Diego, CA, Aug. 16-17, 1999.
26. http://www.ti.com, Texas Instruments, Dallas, TX, USA.
27. L. Hennessy and D.A. Patterson, "Computer Architecture: A Quantitative Approach," (2nd ed.), Morgan Kaufmann Publishers, Inc., San Francisco, CA, 1996.
28. H. Dawid and H. Meyr, "Digital Signal Processing for Multimedia Systems," K. Parhi and T. Nishitani (Eds.), Marcel Dekker Inc., 1999, pp. 623-652.